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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
      • Observed Assertion Sees Previous Cycle
      • Does #0 Beat NBA?
      • Chained #0 Delays vs Single NBA
      • Program Reactive Drive Lag
      • Last NBA in a Process Wins
      • Assertion Action Block Cannot Rewind Edge
    • Race Condition Puzzles
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Concurrency & Timing Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Event Scheduling Puzzles

VLSI DV Interview Puzzles · All levels

Event Scheduling Puzzles

These puzzles force precise reasoning across preponed, active, inactive, NBA, observed, and reactive regions. Most interview misses happen when candidates reason in source-code order instead of scheduler order.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Observed Assertion Sees Previous Cycle1 lesson
  2. 2Does #0 Beat NBA?1 lesson
  3. 3Chained #0 Delays vs Single NBA1 lesson
  4. 4Program Reactive Drive Lag1 lesson
  5. 5Last NBA in a Process Wins1 lesson
  6. 6Assertion Action Block Cannot Rewind Edge1 lesson
On this page

    About this puzzle set

    These puzzles force precise reasoning across preponed, active, inactive, NBA, observed, and reactive regions. Most interview misses happen when candidates reason in source-code order instead of scheduler order.

    Puzzles in this topic

    Diagram
    1. Observed Assertion Sees Previous Cycle  [Medium]
    2. Does #0 Beat NBA?  [Easy]
    3. Chained #0 Delays vs Single NBA  [Medium]
    4. Program Reactive Drive Lag  [Hard]
    5. Last NBA in a Process Wins  [Easy]
    6. Assertion Action Block Cannot Rewind Edge  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    SV scheduling regions at puzzle scale

    Diagram
    SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
    
    time slot T
       |
       +--> ACTIVE   : blocking statements, RHS sampling
       +--> INACTIVE : #0 queued work
       +--> NBA      : non-blocking LHS updates commit
       +--> OBSERVED : assertions sample stable design values
       +--> REACTIVE : testbench/program reaction code
    
    If behavior looks impossible, ask: "Which region saw which value?"

    Related topics

    • Concurrency & Timing Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Race Condition Puzzles
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles