VLSI DV Interview Puzzles · All levels
Event Scheduling Puzzles
These puzzles force precise reasoning across preponed, active, inactive, NBA, observed, and reactive regions. Most interview misses happen when candidates reason in source-code order instead of scheduler order.
About this puzzle set
These puzzles force precise reasoning across preponed, active, inactive, NBA, observed, and reactive regions. Most interview misses happen when candidates reason in source-code order instead of scheduler order.
Puzzles in this topic
diagram
1. Observed Assertion Sees Previous Cycle [Medium]
2. Does #0 Beat NBA? [Easy]
3. Chained #0 Delays vs Single NBA [Medium]
4. Program Reactive Drive Lag [Hard]
5. Last NBA in a Process Wins [Easy]
6. Assertion Action Block Cannot Rewind Edge [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
SV scheduling regions at puzzle scale
diagram
SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
time slot T
|
+--> ACTIVE : blocking statements, RHS sampling
+--> INACTIVE : #0 queued work
+--> NBA : non-blocking LHS updates commit
+--> OBSERVED : assertions sample stable design values
+--> REACTIVE : testbench/program reaction code
If behavior looks impossible, ask: "Which region saw which value?"