VLSI DV Interview Puzzles · All levels
Assertion Action Block Cannot Rewind Edge
The assertion fails and action block drives req<=0. Decide whether that can fix the same failing edge for ack.
Puzzle
Difficulty: Hard · Puzzle 6 of 6 · Topic: Event Scheduling Puzzles
The assertion fails and action block drives req<=0. Decide whether that can fix the same failing edge for ack.
Code
systemverilog
module tb;
bit clk = 0;
bit req = 1;
bit ack = 0;
always #5 clk = ~clk;
always @(posedge clk) ack <= req;
ap_same_cycle: assert property (@(posedge clk) req |-> ack)
else begin
req <= 0;
$display("[%0t REACTIVE] action drives req<=0", $time);
end
initial begin
repeat (3) @(posedge clk);
$finish;
end
endmoduleHint
Assertion action block executes in reactive, after observed failure detection.
Step-by-step solution
diagram
1) At first posedge t=5, ack samples old req and remains 0 for that edge.
2) Property req |-> ack fails at t=5 because req=1 and sampled ack=0.
3) Action block runs in reactive and schedules req<=0 for later in slot.
4) This cannot retroactively change sampled values on the same edge.
5) Effect of req<=0 is visible only from later scheduler phases/next edge behavior.Answer
Answer: No. The action block executes too late to fix the same sampled failure; it only influences future behavior.
Why candidates get it wrong
Treating assertion action blocks as if they execute in active is a common interview trap.
Interviewer follow-up
How would you encode a non-overlapped check that matches this pipeline behavior?