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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
      • Observed Assertion Sees Previous Cycle
      • Does #0 Beat NBA?
      • Chained #0 Delays vs Single NBA
      • Program Reactive Drive Lag
      • Last NBA in a Process Wins
      • Assertion Action Block Cannot Rewind Edge
    • Race Condition Puzzles
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Event Scheduling Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Event Scheduling Puzzles
  5. Assertion Action Block Cannot Rewind Edge

VLSI DV Interview Puzzles · All levels

Assertion Action Block Cannot Rewind Edge

The assertion fails and action block drives req<=0. Decide whether that can fix the same failing edge for ack.

On this page

    Puzzle

    Difficulty: Hard · Puzzle 6 of 6 · Topic: Event Scheduling Puzzles

    The assertion fails and action block drives req<=0. Decide whether that can fix the same failing edge for ack.

    Code

    tb.sv
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    module tb;
      bit clk = 0;
      bit req = 1;
      bit ack = 0;
      always #5 clk = ~clk;
    
      always @(posedge clk) ack <= req;
    
      ap_same_cycle: assert property (@(posedge clk) req |-> ack)
        else begin
          req <= 0;
          $display("[%0t REACTIVE] action drives req<=0", $time);
        end
    
      initial begin
        repeat (3) @(posedge clk);
        $finish;
      end
    endmodule

    Hint

    Assertion action block executes in reactive, after observed failure detection.

    Step-by-step solution

    Diagram
    1) At first posedge t=5, ack samples old req and remains 0 for that edge.
    2) Property req |-> ack fails at t=5 because req=1 and sampled ack=0.
    3) Action block runs in reactive and schedules req<=0 for later in slot.
    4) This cannot retroactively change sampled values on the same edge.
    5) Effect of req<=0 is visible only from later scheduler phases/next edge behavior.

    Answer

    Answer: No. The action block executes too late to fix the same sampled failure; it only influences future behavior.

    Why candidates get it wrong

    Treating assertion action blocks as if they execute in active is a common interview trap.

    Interviewer follow-up

    How would you encode a non-overlapped check that matches this pipeline behavior?

    Related topics

    • Back to Event Scheduling Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Observed Assertion Sees Previous Cycle
    • Does #0 Beat NBA?
    • Chained #0 Delays vs Single NBA