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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
      • Observed Assertion Sees Previous Cycle
      • Does #0 Beat NBA?
      • Chained #0 Delays vs Single NBA
      • Program Reactive Drive Lag
      • Last NBA in a Process Wins
      • Assertion Action Block Cannot Rewind Edge
    • Race Condition Puzzles
    • Clocking Block Puzzles
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Event Scheduling Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Event Scheduling Puzzles
  5. Observed Assertion Sees Previous Cycle

VLSI DV Interview Puzzles · All levels

Observed Assertion Sees Previous Cycle

On the first three rising edges, decide whether the assertion passes or fails. Explain why its result disagrees with post-NBA intuition.

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    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Event Scheduling Puzzles

    On the first three rising edges, decide whether the assertion passes or fails. Explain why its result disagrees with post-NBA intuition.

    Code

    tb.sv
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    module tb;
      bit clk = 0;
      bit a = 0, b = 0;
    
      always #5 clk = ~clk;
    
      always @(posedge clk) begin
        a <= ~a;
        b <= a;
        $display("[%0t ACTIVE] a=%0b b=%0b", $time, a, b);
      end
    
      ap_align: assert property (@(posedge clk) b == a)
        else $error("[%0t OBSERVED] sampled mismatch: b != a", $time);
    
      initial begin
        repeat (3) @(posedge clk);
        $finish;
      end
    endmodule

    Hint

    Concurrent assertions sample in preponed, not after NBAs.

    Step-by-step solution

    Diagram
    1) At t=5, sampled values are a=0 and b=0, so assertion passes.
    2) The always block then schedules a<=1 and b<=0 in NBA.
    3) At t=15, sampled values are a=1 and b=0 from previous cycle state, so assertion fails.
    4) At t=25, sampled values are a=0 and b=1, so it fails again.
    5) Observed-region evaluation still uses preponed sampled data.

    Answer

    Answer: Pass at t=5, fail at t=15 and t=25. The assertion compares preponed samples, so it effectively checks previous-cycle relationship, not same-edge post-NBA values.

    Why candidates get it wrong

    Equating observed evaluation time with observed sampling time is wrong; sampling already happened earlier.

    Interviewer follow-up

    How would you rewrite the property to intentionally compare against previous-cycle a using $past?

    Related topics

    • Back to Event Scheduling Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Chained #0 Delays vs Single NBA
    • Program Reactive Drive Lag
    • Last NBA in a Process Wins