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  2. DV Interview Puzzles

DV Interview Puzzles

All courses

Intermediate · ~6 h · 210 lessons · 9 sections

Drill interview puzzles: races, fork/join and datatype traps.

Start courseHow to Use This Puzzle Bank

Course map

  1. How to Use This Puzzle Bank
    1 lesson

    Starts with How to Use This Puzzle Bank

  2. SystemVerilog Language Puzzles
    25 lessons

    Starts with X-Bit Comparisons and Mixed Arithmetic

  3. Difficulty Guide
    1 lesson

    Starts with Difficulty Guide

  4. Full Topic Map
    1 lesson

    Starts with Full Topic Map

  5. Interview-Day Tips
    1 lesson

    Starts with Interview-Day Tips

  6. OOP & Testbench Puzzles
    25 lessons

    Starts with Shallow Copy in Nested Payload

  7. Concurrency & Timing Puzzles
    25 lessons

    Starts with Observed Assertion Sees Previous Cycle

  8. Randomization & Constraint Puzzles
    25 lessons

    Starts with Implication vs Partitioned Branches

  9. SVA Assertion Puzzles
    25 lessons

    Starts with Exact Delay Then Bounded Hold

  10. Functional Coverage Puzzles
    25 lessons

    Starts with Auto vs explicit bins with illegal transition context

  11. Logic & Aptitude Puzzles
    25 lessons

    Starts with 9 Balls, 1 Heavier, 2 Weighings

  12. Scenario & Debug Puzzles
    25 lessons

    Starts with Handshake Hang: Missing item_done on One Branch

  13. Interview Prep: Puzzle Rounds
    5 lessons

    Starts with Framework for Any Unseen Puzzle

  14. DV Puzzle Cheatsheet
    1 lesson

    Starts with DV Puzzle Cheatsheet

About this course

What this course is

This is a puzzle bank, not a lecture series. Every page is a real interview-style puzzle. You get the prompt and code first; predict the answer, then check the worked solution, the exact answer, and the specific trap interviewers are testing.

  • 192 worked puzzles across 8 themes (24 per theme, 6 per topic).

  • Each puzzle: prompt, code, hint, step-by-step solution, exact answer, gotcha, and a follow-up question.

  • Difficulty tags (Easy / Medium / Hard) so you can ramp up the way interviewers escalate.

  • Section Q&A and interview-round walkthroughs to rehearse explaining your reasoning out loud.

The 8 puzzle themes

Show how the course is organised
Diagram
1. SystemVerilog Language Puzzles (4 topics, 24 puzzles)
2. OOP & Testbench Puzzles (4 topics, 24 puzzles)
3. Concurrency & Timing Puzzles (4 topics, 24 puzzles)
4. Randomization & Constraint Puzzles (4 topics, 24 puzzles)
5. SVA Assertion Puzzles (4 topics, 24 puzzles)
6. Functional Coverage Puzzles (4 topics, 24 puzzles)
7. Logic & Aptitude Puzzles (4 topics, 24 puzzles)
8. Scenario & Debug Puzzles (4 topics, 24 puzzles)

How to use it

  1. Pick a theme and open a topic.

  2. Read the puzzle prompt and code; write down your predicted answer before scrolling.

  3. Open the puzzle page, compare with the worked solution and exact answer.

  4. Read the gotcha and follow-up — that is what separates a pass from a fail.

Related topics

  • SystemVerilog course
  • SystemVerilog OOP Mastery
  • UVM Verification course
  • Verification IP & Protocol Compliance
Open question bankPractice questions for this track