VLSI DV Interview Puzzles · All levels

Auto vs explicit bins with illegal transition context

Predict bin counts and final coverage for all three coverpoints after this sample sequence. Explain why one sampled value raises an error but does not improve legal coverage.

Puzzle

Difficulty: Medium · Puzzle 1 of 6 · Topic: Covergroup and Coverpoint Puzzles

Predict bin counts and final coverage for all three coverpoints after this sample sequence. Explain why one sampled value raises an error but does not improve legal coverage.

Code

systemverilog
covergroup cg with function sample(bit [1:0] mode, bit [1:0] state);
  cp_mode_auto: coverpoint mode;

  cp_mode_exp: coverpoint mode {
    bins idle_or_cfg = {0,1};
    bins run         = {2};
    illegal_bins bad = {3};
  }

  cp_state_tr: coverpoint state {
    bins up   = (0 => 1 => 2);
    bins down = (2 => 1 => 0);
  }
endgroup

initial begin
  cg c = new();
  c.sample(0,0);
  c.sample(1,1);
  c.sample(2,2);
  c.sample(3,1);
  c.sample(2,0);
end

Hint

Count legal bins only for cp_mode_exp, then derive transition sequence from sampled state values 0,1,2,1,0.

Step-by-step solution

diagram
1) cp_mode_auto has 4 auto bins (0,1,2,3) and all are hit -> 4/4 = 100%.
2) cp_mode_exp has 2 legal bins (idle_or_cfg, run); both are hit -> 2/2 = 100%.
3) mode=3 hits illegal_bins bad and is reported as illegal activity, not legal progress.
4) cp_state_tr sees sampled states 0,1,2,1,0 so both up and down transitions occur -> 2/2 = 100%.

Answer

Answer: cp_mode_auto: 4/4 = 100%. cp_mode_exp: legal coverage 2/2 = 100% with one illegal hit on value 3. cp_state_tr: 2/2 = 100%.

Why candidates get it wrong

Illegal bins are correctness alarms. They do not increase legal numerator or denominator, so they cannot close functional coverage.

Interviewer follow-up

If the simulator is configured to stop on illegal_bins, how would that change your closure strategy and test ordering?

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