VLSI DV Interview Puzzles · All levels

Transition bin sequence counting

Determine which transition bins hit and give final percentage.

Puzzle

Difficulty: Medium · Puzzle 4 of 6 · Topic: Covergroup and Coverpoint Puzzles

Determine which transition bins hit and give final percentage.

Code

systemverilog

covergroup cg with function sample(bit [1:0] state);
  cp_state: coverpoint state {
    bins warmup = (0 => 1 => 2);
    bins bounce = (2 => 1 => 2);
    bins reset  = (2 => 0);
  }
endgroup

initial begin
  cg c = new();
  c.sample(0);
  c.sample(1);
  c.sample(2);
  c.sample(1);
  c.sample(2);
  c.sample(0);
end

Hint

Write the sampled stream first, then slide windows for 3-step and 2-step transitions.

Step-by-step solution

diagram

1) Sampled stream is 0,1,2,1,2,0.
2) warmup (0=>1=>2) matches at samples 1..3.
3) bounce (2=>1=>2) matches at samples 3..5.
4) reset (2=>0) matches at samples 5..6.
5) All 3 bins hit -> 3/3 = 100%.

Answer

Answer: warmup, bounce, and reset all hit, so coverage is 100% (3/3).

Why candidates get it wrong

Candidates often count only non-overlapping windows and miss valid overlapping transition matches.

Interviewer follow-up

How many bins remain hit if the last sample c.sample(0) is removed?

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