Interview-style SystemVerilog/UVM OOP puzzles focused on bugs that appear in real verification code, not classroom examples. The set drills deep-copy correctness, dispatch semantics through base handles, parameterized-class specialization behavior, and exact UVM factory override resolution. Each topic is designed for board-style interviews where you must predict behavior and justify it quickly.
Handle and Copy Puzzles — 6 puzzles
Virtual Method Puzzles — 6 puzzles
Parameterized Class Puzzles — 6 puzzles
Factory Override Puzzles — 6 puzzlesOpen each topic and attempt every puzzle cold, writing your predicted answer first.
Only then read the step-by-step solution and confirm the exact answer.
Re-read the 'why candidates get it wrong' note — that is the actual interview signal.
Finish with the section Q&A to rehearse explaining the rule out loud.