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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
    • Handle and Copy Puzzles
    • Virtual Method Puzzles
    • Parameterized Class Puzzles
    • Factory Override Puzzles
      • Type Override vs Instance Override Specificity
      • create() Honors Override, new() Bypasses
      • Replace Flag in Repeated set_type_override
      • Wildcard Instance Path Precedence
      • Component Override in build_phase
      • Override Timing Relative to create Calls
    • OOP & Testbench Puzzles: Tricky Q&A
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹OOP & Testbench Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. OOP & Testbench Puzzles
  4. Factory Override Puzzles

VLSI DV Interview Puzzles · All levels

Factory Override Puzzles

These puzzles test exact UVM factory behavior under competing overrides and mixed object creation styles. You must reason about precedence, path specificity, timing of override registration, and the critical difference between `create()` and direct `new()`.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Type Override vs Instance Override Specificity1 lesson
  2. 2create() Honors Override, new() Bypasses1 lesson
  3. 3Replace Flag in Repeated set_type_override1 lesson
  4. 4Wildcard Instance Path Precedence1 lesson
  5. 5Component Override in build_phase1 lesson
  6. 6Override Timing Relative to create Calls1 lesson
On this page

    About this puzzle set

    These puzzles test exact UVM factory behavior under competing overrides and mixed object creation styles. You must reason about precedence, path specificity, timing of override registration, and the critical difference between `create()` and direct `new()`.

    Puzzles in this topic

    Diagram
    1. Type Override vs Instance Override Specificity  [Medium]
    2. create() Honors Override, new() Bypasses  [Easy]
    3. Replace Flag in Repeated set_type_override  [Medium]
    4. Wildcard Instance Path Precedence  [Hard]
    5. Component Override in build_phase  [Medium]
    6. Override Timing Relative to create Calls  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    fork/join variants and completion semantics

    Diagram
    FORK/JOIN INTERVIEW CHEAT MAP
    
    fork
      task_a();   // 3 cycles
      task_b();   // 1 cycle
    join
    --> parent waits for all children
    
    fork ... join_any
    --> parent continues after first child completes
    
    fork ... join_none
    --> parent continues immediately; children run detached
    
    Use wait fork; later to synchronize detached threads.

    Related topics

    • OOP & Testbench Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Type Override vs Instance Override Specificity

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    See also

    • Handle and Copy Puzzles
    • Virtual Method Puzzles
    • Parameterized Class Puzzles