VLSI DV Interview Puzzles · All levels

Component Override in build_phase

Two env variants construct `agent` differently in `build_phase`. Which one honors test-level component override?

Puzzle

Difficulty: Medium · Puzzle 5 of 6 · Topic: Factory Override Puzzles

Two env variants construct `agent` differently in `build_phase`. Which one honors test-level component override?

Code

systemverilog

class agent extends uvm_component;
  `uvm_component_utils(agent)
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
endclass
class agent_ext extends agent;
  `uvm_component_utils(agent_ext)
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
endclass

class env_a extends uvm_env;
  `uvm_component_utils(env_a)
  agent agt;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agt = agent::type_id::create("agt", this);
  endfunction
endclass

class env_b extends uvm_env;
  `uvm_component_utils(env_b)
  agent agt;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    agt = new("agt", this);
  endfunction
endclass

Hint

Component overrides require factory path; direct constructor call skips factory.

Step-by-step solution

diagram

1) `env_a` uses `type_id::create`, so override `agent -> agent_ext` is honored.
2) `env_b` uses direct `new`, so override is bypassed.
3) Result: env_a gets `agent_ext`, env_b gets `agent`.

Answer

Answer: Only `env_a` honors component override because it constructs through factory `create`.

Why candidates get it wrong

Direct component `new` in build_phase is a frequent reason overrides 'mysteriously' do nothing.

Interviewer follow-up

Would this differ for objects created in `run_phase` versus components in `build_phase`?

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