Full Topic Map

SystemVerilog Language Puzzles
   - Datatype and Bit Puzzles (6)
   - Fork Join Puzzles (6)
   - Queue and Array Puzzles (6)
   - String and Casting Puzzles (6)

OOP & Testbench Puzzles
   - Handle and Copy Puzzles (6)
   - Virtual Method Puzzles (6)
   - Parameterized Class Puzzles (6)
   - Factory Override Puzzles (6)

Concurrency & Timing Puzzles
   - Event Scheduling Puzzles (6)
   - Race Condition Puzzles (6)
   - Clocking Block Puzzles (6)
   - Semaphore & Mailbox Puzzles (6)

Randomization & Constraint Puzzles
   - Constraint Solving Order Puzzles (6)
   - Distribution Puzzles (`dist`, `:=` vs `:/`) (6)
   - solve...before Bias Puzzles (6)
   - randomize() with Puzzles (6)

SVA Assertion Puzzles
   - Sequence Puzzles (6)
   - Implication Puzzles (6)
   - Temporal Corner Puzzles (6)
   - Assertion Debug Puzzles (6)

Functional Coverage Puzzles
   - Covergroup and Coverpoint Puzzles (6)
   - Cross Coverage Puzzles (6)
   - Coverage Options Puzzles (6)
   - Coverage Closure and Sampling Timing Puzzles (6)

Logic & Aptitude Puzzles
   - Classic Brain Teasers (6)
   - Probability Puzzles (6)
   - Digital Logic Puzzles (6)
   - Debugging Riddles (6)

Scenario & Debug Puzzles
   - Testbench Debug Puzzles: Why Did the Test Hang? (6)
   - Deadlock Scenario Puzzles: Objection and Phase Stalls (6)
   - Scoreboard Puzzles: Mismatch or Ordering Bug? (6)
   - Real Interview Rounds: End-to-End Debug Walkthrough (6)