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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
    • Real Interview Rounds: End-to-End Debug Walkthrough
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹DV Interview Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles

VLSI DV Interview Puzzles · All levels

Scenario & Debug Puzzles

Puzzle-centric DV interview section focused on realistic UVM/TB failures: hangs, phase deadlocks, scoreboard false mismatches, and structured live-debug rounds.

  • 5topics
  • 25lessons

Topics in this section

  1. 1Testbench Debug Puzzles: Why Did the Test Hang?6 lessons
    • Handshake Hang: Missing item_done on One Branch
    • Missing run_phase Objection in Test
    • Wrong Phase: Starting Traffic in shutdown_phase
    • Handshake Violation: item_done Called Twice
    • Sequence get_response Stall
    • Virtual Sequence Waits on Event Never Triggered
  2. 2Deadlock Scenario Puzzles: Objection and Phase Stalls6 lessons
    • Early Return Leaves Objection Raised
    • fork...join_none Thread Leak
    • Semaphore Token Leak on Error Path
    • Mailbox Consumer Blocks Forever
    • Lock Inversion with Two Semaphores
    • Child Sequence Raises Objection but Never Drops
  3. 3Scoreboard Puzzles: Mismatch or Ordering Bug?6 lessons
    • Out-of-Order Responses Miscompared as Corruption
    • Missing First Transaction After Reset
    • Duplicate Transactions from Handle Reuse
    • Mismatch Cascade from Incorrect Pop Policy
    • End-of-Test Draining Missing
    • Duplicate Expected Entries from Predictor Retry Path
  4. 4Real Interview Rounds: End-to-End Debug Walkthrough6 lessons
    • Round Walkthrough: Sequencer Waits for item_done
    • Round Walkthrough: Objection Deadlock with Clean Waves
    • Round Walkthrough: APB Reads Return Previous Data
    • Round Walkthrough: Out-of-Order Channel Mismatch
    • Round Walkthrough: Rare Parallel Deadlock
    • Round Walkthrough: End-of-Test False Fail
  5. 5Scenario & Debug Puzzles: Tricky Q&A1 lesson
On this page

    What this section covers

    Puzzle-centric DV interview section focused on realistic UVM/TB failures: hangs, phase deadlocks, scoreboard false mismatches, and structured live-debug rounds.

    Topics

    Diagram
    Testbench Debug Puzzles: Why Did the Test Hang? — 6 puzzles
    Deadlock Scenario Puzzles: Objection and Phase Stalls — 6 puzzles
    Scoreboard Puzzles: Mismatch or Ordering Bug? — 6 puzzles
    Real Interview Rounds: End-to-End Debug Walkthrough — 6 puzzles

    How to practice

    1. Open each topic and attempt every puzzle cold, writing your predicted answer first.

    2. Only then read the step-by-step solution and confirm the exact answer.

    3. Re-read the 'why candidates get it wrong' note — that is the actual interview signal.

    4. Finish with the section Q&A to rehearse explaining the rule out loud.

    Related topics

    • VLSI DV Interview Puzzles hub

    PreviousNext: Testbench Debug Puzzles: Why Did the Test Hang?

    Up next

    Up nextTestbench Debug Puzzles: Why Did the Test Hang?

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    See also

    • How to Use This Puzzle Bank
    • SystemVerilog Language Puzzles
    • Difficulty Guide