Scenario & Debug Puzzles

What this section covers

Puzzle-centric DV interview section focused on realistic UVM/TB failures: hangs, phase deadlocks, scoreboard false mismatches, and structured live-debug rounds.

Topics

Testbench Debug Puzzles: Why Did the Test Hang? — 6 puzzles
Deadlock Scenario Puzzles: Objection and Phase Stalls — 6 puzzles
Scoreboard Puzzles: Mismatch or Ordering Bug? — 6 puzzles
Real Interview Rounds: End-to-End Debug Walkthrough — 6 puzzles

How to practice

1. Open each topic and attempt every puzzle cold, writing your predicted answer first.

2. Only then read the step-by-step solution and confirm the exact answer.

3. Re-read the 'why candidates get it wrong' note — that is the actual interview signal.

4. Finish with the section Q&A to rehearse explaining the rule out loud.

Related topics

• VLSI DV Interview Puzzles hub