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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
    • Real Interview Rounds: End-to-End Debug Walkthrough
      • Round Walkthrough: Sequencer Waits for item_done
      • Round Walkthrough: Objection Deadlock with Clean Waves
      • Round Walkthrough: APB Reads Return Previous Data
      • Round Walkthrough: Out-of-Order Channel Mismatch
      • Round Walkthrough: Rare Parallel Deadlock
      • Round Walkthrough: End-of-Test False Fail
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Real Interview Rounds: End-to-End Debug Walkthrough
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Real Interview Rounds: End-to-End Debug Walkthrough
  5. Round Walkthrough: Out-of-Order Channel Mismatch

VLSI DV Interview Puzzles · All levels

Round Walkthrough: Out-of-Order Channel Mismatch

Interviewer provides logs with mismatch bursts under high concurrency only. Demonstrate a complete round that proves checker-model issue, not DUT corruption.

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    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Real Interview Rounds: End-to-End Debug Walkthrough

    Interviewer provides logs with mismatch bursts under high concurrency only. Demonstrate a complete round that proves checker-model issue, not DUT corruption.

    Code

    design.sv
    1
    2
    3
    4
    5
    exp_fifo.get(exp);
    got_fifo.get(got);
    if (!exp.compare(got))
      \`uvm_error("SB", "mismatch");
    // protocol note: responses may return out of order by tag

    Hint

    Show how you ask for protocol guarantees before editing scoreboard logic.

    Step-by-step solution

    Diagram
    1) Symptom: mismatch frequency rises with parallel outstanding transactions.
    2) Hypotheses: data corruption, monitor reorder, or scoreboard ordering assumption bug.
    3) Instrumentation: log compare pairs with tag/id and outstanding depth.
    4) Root cause: strict FIFO compare conflicts with legal out-of-order response behavior.
    5) Fix + validation: match by tag/id map and pass directed reorder stress tests.

    Answer

    Answer: Actual bug: scoreboard uses in-order compare for an out-of-order protocol. Fix: key matches by transaction tag and keep timeout for unmatched entries.

    Why candidates get it wrong

    If you skip protocol clarification, you may 'fix' the DUT for a checker mistake.

    Interviewer follow-up

    What data structure would you use for high-throughput keyed matching and why?

    Related topics

    • Back to Real Interview Rounds: End-to-End Debug Walkthrough

    • Scenario & Debug Puzzles section

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    See also

    • Round Walkthrough: Sequencer Waits for item_done
    • Round Walkthrough: Objection Deadlock with Clean Waves
    • Round Walkthrough: End-of-Test False Fail