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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
    • Real Interview Rounds: End-to-End Debug Walkthrough
      • Round Walkthrough: Sequencer Waits for item_done
      • Round Walkthrough: Objection Deadlock with Clean Waves
      • Round Walkthrough: APB Reads Return Previous Data
      • Round Walkthrough: Out-of-Order Channel Mismatch
      • Round Walkthrough: Rare Parallel Deadlock
      • Round Walkthrough: End-of-Test False Fail
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Real Interview Rounds: End-to-End Debug Walkthrough
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Real Interview Rounds: End-to-End Debug Walkthrough
  5. Round Walkthrough: End-of-Test False Fail

VLSI DV Interview Puzzles · All levels

Round Walkthrough: End-of-Test False Fail

Round setup: scoreboard fails at test end with 2 pending expected entries. DUT latency is variable and responses can arrive shortly after stimulus ends.

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    Puzzle

    Difficulty: Hard · Puzzle 6 of 6 · Topic: Real Interview Rounds: End-to-End Debug Walkthrough

    Round setup: scoreboard fails at test end with 2 pending expected entries. DUT latency is variable and responses can arrive shortly after stimulus ends.

    Code

    design.sv
    1
    2
    3
    4
    function void check_phase(uvm_phase phase);
      if (exp_q.size() != 0)
        \`uvm_error("SB", $sformatf("pending exp=%0d", exp_q.size()));
    endfunction

    Hint

    End-of-test policy is part of checker correctness.

    Step-by-step solution

    Diagram
    1) Symptom: sporadic pending expected entries at check_phase.
    2) Hypotheses: dropped monitor item, predictor overcount, or missing drain window.
    3) Instrumentation: trace queue depths from last stimulus to phase end.
    4) Root cause: check_phase executes before legal late responses are drained.
    5) Fix + validation: add bounded drain in phase_ready_to_end with progress/timeout logging.

    Answer

    Answer: Actual bug: no end-of-test drain policy for elastic latency. Fix: hold phase briefly and drain queues with timeout rather than immediate hard fail.

    Why candidates get it wrong

    Blindly increasing timeout can hide real leaks; bounded drain with diagnostics is required.

    Interviewer follow-up

    What metrics would you log to prove drain time is healthy and not masking a deadlock?

    Related topics

    • Back to Real Interview Rounds: End-to-End Debug Walkthrough

    • Scenario & Debug Puzzles section

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    See also

    • Round Walkthrough: Sequencer Waits for item_done
    • Round Walkthrough: Objection Deadlock with Clean Waves
    • Round Walkthrough: APB Reads Return Previous Data