VLSI DV Interview Puzzles · All levels

Round Walkthrough: End-of-Test False Fail

Round setup: scoreboard fails at test end with 2 pending expected entries. DUT latency is variable and responses can arrive shortly after stimulus ends.

Puzzle

Difficulty: Hard · Puzzle 6 of 6 · Topic: Real Interview Rounds: End-to-End Debug Walkthrough

Round setup: scoreboard fails at test end with 2 pending expected entries. DUT latency is variable and responses can arrive shortly after stimulus ends.

Code

systemverilog

function void check_phase(uvm_phase phase);
  if (exp_q.size() != 0)
    \`uvm_error("SB", $sformatf("pending exp=%0d", exp_q.size()));
endfunction

Hint

End-of-test policy is part of checker correctness.

Step-by-step solution

diagram

1) Symptom: sporadic pending expected entries at check_phase.
2) Hypotheses: dropped monitor item, predictor overcount, or missing drain window.
3) Instrumentation: trace queue depths from last stimulus to phase end.
4) Root cause: check_phase executes before legal late responses are drained.
5) Fix + validation: add bounded drain in phase_ready_to_end with progress/timeout logging.

Answer

Answer: Actual bug: no end-of-test drain policy for elastic latency. Fix: hold phase briefly and drain queues with timeout rather than immediate hard fail.

Why candidates get it wrong

Blindly increasing timeout can hide real leaks; bounded drain with diagnostics is required.

Interviewer follow-up

What metrics would you log to prove drain time is healthy and not masking a deadlock?

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