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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
      • Out-of-Order Responses Miscompared as Corruption
      • Missing First Transaction After Reset
      • Duplicate Transactions from Handle Reuse
      • Mismatch Cascade from Incorrect Pop Policy
      • End-of-Test Draining Missing
      • Duplicate Expected Entries from Predictor Retry Path
    • Real Interview Rounds: End-to-End Debug Walkthrough
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Scenario & Debug Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Scoreboard Puzzles: Mismatch or Ordering Bug?

VLSI DV Interview Puzzles · All levels

Scoreboard Puzzles: Mismatch or Ordering Bug?

Separate DUT bugs from checker-model bugs: ordering policy, duplication, drops, and end-of-test drain.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Out-of-Order Responses Miscompared as Corruption1 lesson
  2. 2Missing First Transaction After Reset1 lesson
  3. 3Duplicate Transactions from Handle Reuse1 lesson
  4. 4Mismatch Cascade from Incorrect Pop Policy1 lesson
  5. 5End-of-Test Draining Missing1 lesson
  6. 6Duplicate Expected Entries from Predictor Retry Path1 lesson
On this page

    About this puzzle set

    Separate DUT bugs from checker-model bugs: ordering policy, duplication, drops, and end-of-test drain.

    Puzzles in this topic

    Diagram
    1. Out-of-Order Responses Miscompared as Corruption  [Medium]
    2. Missing First Transaction After Reset  [Medium]
    3. Duplicate Transactions from Handle Reuse  [Easy]
    4. Mismatch Cascade from Incorrect Pop Policy  [Hard]
    5. End-of-Test Draining Missing  [Hard]
    6. Duplicate Expected Entries from Predictor Retry Path  [Medium]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • Scenario & Debug Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Out-of-Order Responses Miscompared as Corruption

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    Up nextOut-of-Order Responses Miscompared as Corruption

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    See also

    • Testbench Debug Puzzles: Why Did the Test Hang?
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Real Interview Rounds: End-to-End Debug Walkthrough