VLSI DV Interview Puzzles · All levels

End-of-Test Draining Missing

Random tests fail with 'expected queue not empty' in about 2% seeds. DUT has variable response latency and can legally return after stimulus stops.

Puzzle

Difficulty: Hard · Puzzle 5 of 6 · Topic: Scoreboard Puzzles: Mismatch or Ordering Bug?

Random tests fail with 'expected queue not empty' in about 2% seeds. DUT has variable response latency and can legally return after stimulus stops.

Code

systemverilog

task run_phase(uvm_phase phase);
  forever begin
    compare_once();
  end
endtask

function void check_phase(uvm_phase phase);
  if (exp_q.size() != 0 || got_q.size() != 0)
    \`uvm_error("SB", "leftover transactions");
endfunction

Hint

A scoreboard needs explicit drain policy when response latency is elastic.

Step-by-step solution

diagram

1) Log queue sizes near end-of-test and observe they are shrinking but not yet zero.
2) Confirm no drain window exists between stimulus completion and final check.
3) Implement phase_ready_to_end wait/drain with bounded timeout and progress checks.
4) Keep objection until queues settle or timeout indicates real hang.
5) Track residual ids in timeout message for actionable debug.

Answer

Answer: Bug: scoreboard checks leftovers immediately without allowing legal late responses to drain. Fix: add bounded end-of-test draining before final emptiness assertion.

Why candidates get it wrong

Removing the check hides escapes; the right fix is controlled drain, not silence.

Interviewer follow-up

What timeout heuristic would you use so drain does not mask real deadlocks?

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