VLSI DV Interview Puzzles · All levels

Missing First Transaction After Reset

Scoreboard reports one missing response per test, always near reset release. DUT waveform shows the response is produced.

Puzzle

Difficulty: Medium · Puzzle 2 of 6 · Topic: Scoreboard Puzzles: Mismatch or Ordering Bug?

Scoreboard reports one missing response per test, always near reset release. DUT waveform shows the response is produced.

Code

systemverilog

function void mon::write_rsp(bus_rsp r);
  if (!vif.rst_n)
    return;
  if (r.valid)
    rsp_ap.write(r);
endfunction

always @(posedge vif.clk) begin
  if (vif.rst_n && dut_rsp_valid)
    sampled_rsp.valid <= 1'b1; // first post-reset cycle is valid
end

Hint

Reset gating in monitor can be off-by-one relative to interface sampling.

Step-by-step solution

diagram

1) Correlate first missing transaction timestamp with reset deassertion edge.
2) Compare monitor sampling phase to DUT valid generation phase.
3) Observe monitor return condition drops first legal post-reset response.
4) Align reset gating with sampled protocol validity (clocking block or one-cycle grace).
5) Add reset-boundary directed test to prevent reintroduction.

Answer

Answer: Bug: monitor reset filter drops a valid first post-reset response, causing scoreboard missing-item error. Fix: align reset gating/sampling so legal boundary response is captured.

Why candidates get it wrong

Teams often blame predictor or DUT queue depth while monitor gating is the true source.

Interviewer follow-up

Would you solve this with clocking block skew, sampled reset, or protocol-state machine in monitor?

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