VLSI DV Interview Puzzles · All levels

Scenario & Debug Puzzles: Tricky Q&A

Rapid-fire interview Q&A for Scenario & Debug Puzzles.

Section Q&A

Rapid-fire questions an interviewer asks around Scenario & Debug Puzzles. Answer out loud, then check yourself.

Q1. A UVM test hangs and the sequencer waits forever. What should you check first?

Answer: Validate handshake liveness first: every get_next_item must lead to exactly one item_done on every control path. This quickly isolates the highest-frequency TB hang bug class.

Trap: Starting with random timeout increases and broad seed reruns before validating handshake pairing.

Q2. How do you quickly separate objection deadlock from long but healthy runtime?

Answer: Turn on \`+UVM_OBJECTION_TRACE\`, identify the exact owner holding objections, and correlate with forward-progress counters (transaction movement, phase transitions). No progress plus held objection indicates deadlock.

Trap: Using wall-clock duration alone as proof of deadlock.

Q3. In scoreboard debug, what pattern avoids blaming DUT too early?

Answer: Classify failure as value, timing, ordering, or accounting issue first. Then verify protocol ordering guarantees and monitor/predictor contracts before concluding DUT data corruption.

Trap: Treating every mismatch print as direct evidence of DUT logic failure.

Q4. What interview answer format scores best in live debug rounds?

Answer: Use a 5-stage flow: symptom, ranked hypotheses, minimal instrumentation plan, proven root cause, and fix plus regression guardrail. It shows both technical depth and debugging leadership.

Trap: Jumping to a speculative code patch without presenting evidence and validation.