Hands-on interview puzzles that force precise reasoning about SystemVerilog semantics, not memorized rules. The set emphasizes 4-state versus 2-state behavior, signed/unsigned and casting traps, fork-join process lifetime control, collection mutation semantics, and runtime typing with string APIs and $cast.
Datatype and Bit Puzzles — 6 puzzles
Fork Join Puzzles — 6 puzzles
Queue and Array Puzzles — 6 puzzles
String and Casting Puzzles — 6 puzzlesOpen each topic and attempt every puzzle cold, writing your predicted answer first.
Only then read the step-by-step solution and confirm the exact answer.
Re-read the 'why candidates get it wrong' note — that is the actual interview signal.
Finish with the section Q&A to rehearse explaining the rule out loud.