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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Case Equality vs Wildcard Equality
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. Type Cast Controls Sign Extension

VLSI DV Interview Puzzles · All levels

Type Cast Controls Sign Extension

Predict `a`, `b`, and `c`. Why are `b` and `c` different from `a`?

On this page

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: Datatype and Bit Puzzles

    Predict `a`, `b`, and `c`. Why are `b` and `c` different from `a`?

    Code

    p3.sv
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    module p3;
      logic [7:0] u8 = 8'h80;
      logic signed [15:0] a, b, c;
      initial begin
        a = u8;
        b = signed'(u8);
        c = $signed(u8);
        $display("a=%0d b=%0d c=%0d", a, b, c);
      end
    endmodule

    Hint

    Assignment from unsigned extends with zeros. `signed'(...)` and `$signed(...)` reinterpret source sign first, then assignment extends.

    Step-by-step solution

    Diagram
    1) `a = u8` zero-extends 8'h80 into 16'h0080, which is +128.
    2) `signed'(u8)` treats the 8-bit pattern as signed before assignment, so 8'h80 is -128 and sign-extends to 16'hFF80.
    3) `$signed(u8)` has the same signed reinterpretation effect here, so `c` is also -128.

    Answer

    Answer: a=128, b=-128, c=-128

    Why candidates get it wrong

    Many candidates assume destination signedness alone decides extension behavior.

    Interviewer follow-up

    What value would `b` have if `u8` were `8'h7F` instead?

    Related topics

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

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    See also

    • X-Bit Comparisons and Mixed Arithmetic
    • X Collapse into 2-State `int`
    • Case Equality vs Wildcard Equality