VLSI DV Interview Puzzles · All levels

Type Cast Controls Sign Extension

Predict `a`, `b`, and `c`. Why are `b` and `c` different from `a`?

Puzzle

Difficulty: Medium · Puzzle 3 of 6 · Topic: Datatype and Bit Puzzles

Predict `a`, `b`, and `c`. Why are `b` and `c` different from `a`?

Code

systemverilog

module p3;
  logic [7:0] u8 = 8'h80;
  logic signed [15:0] a, b, c;
  initial begin
    a = u8;
    b = signed'(u8);
    c = $signed(u8);
    $display("a=%0d b=%0d c=%0d", a, b, c);
  end
endmodule

Hint

Assignment from unsigned extends with zeros. `signed'(...)` and `$signed(...)` reinterpret source sign first, then assignment extends.

Step-by-step solution

diagram

1) `a = u8` zero-extends 8'h80 into 16'h0080, which is +128.
2) `signed'(u8)` treats the 8-bit pattern as signed before assignment, so 8'h80 is -128 and sign-extends to 16'hFF80.
3) `$signed(u8)` has the same signed reinterpretation effect here, so `c` is also -128.

Answer

Answer: a=128, b=-128, c=-128

Why candidates get it wrong

Many candidates assume destination signedness alone decides extension behavior.

Interviewer follow-up

What value would `b` have if `u8` were `8'h7F` instead?

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