VLSI DV Interview Puzzles · All levels

Signed Part-Select Is Still Unsigned

Explain why these three lines are not all the same numeric value.

Puzzle

Difficulty: Hard · Puzzle 4 of 6 · Topic: Datatype and Bit Puzzles

Explain why these three lines are not all the same numeric value.

Code

systemverilog

module p4;
  logic signed [7:0] s = -8'sd2; // 1111_1110
  initial begin
    $display("slice=%0d", s[7:4]);
    $display("signed_slice=%0d", $signed(s[7:4]));
    $display("shift=%0d", s >>> 4);
  end
endmodule

Hint

Part-select expressions lose signedness unless you cast them. `>>>` uses the signedness of the left operand.

Step-by-step solution

diagram

1) `s[7:4]` is 4'b1111 but a part-select expression is unsigned by default, so decimal is 15.
2) `$signed(s[7:4])` reinterprets 4'b1111 as signed -1.
3) `s >>> 4` arithmetic-shifts signed -2 to -1, so it matches line 2, not line 1.

Answer

Answer: slice=15, signed_slice=-1, shift=-1

Why candidates get it wrong

People expect signedness to propagate automatically through slices of signed vectors.

Interviewer follow-up

How would `s >> 4` differ from `s >>> 4` in this example?

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