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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
    • Fork Join Puzzles
      • join vs join_any vs join_none
      • Loop Variable Capture in Detached Threads
      • wait fork Synchronization Point
      • disable Named Fork Scope
      • join_any Without Cleanup
      • Inner disable fork Does Not Kill Outer Sibling
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹SystemVerilog Language Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Fork Join Puzzles

VLSI DV Interview Puzzles · All levels

Fork Join Puzzles

These puzzles test process-lifetime reasoning under real simulator scheduling. You need to predict when parent code resumes, which child threads keep running, and exactly what scope `disable fork` can terminate.

  • 6topics
  • 6lessons

Topics in this section

  1. 1join vs join_any vs join_none1 lesson
  2. 2Loop Variable Capture in Detached Threads1 lesson
  3. 3wait fork Synchronization Point1 lesson
  4. 4disable Named Fork Scope1 lesson
  5. 5join_any Without Cleanup1 lesson
  6. 6Inner disable fork Does Not Kill Outer Sibling1 lesson
On this page

    About this puzzle set

    These puzzles test process-lifetime reasoning under real simulator scheduling. You need to predict when parent code resumes, which child threads keep running, and exactly what scope `disable fork` can terminate.

    Puzzles in this topic

    Diagram
    1. join vs join_any vs join_none  [Easy]
    2. Loop Variable Capture in Detached Threads  [Medium]
    3. wait fork Synchronization Point  [Easy]
    4. disable Named Fork Scope  [Hard]
    5. join_any Without Cleanup  [Medium]
    6. Inner disable fork Does Not Kill Outer Sibling  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    SV scheduling regions at puzzle scale

    Diagram
    SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
    
    time slot T
       |
       +--> ACTIVE   : blocking statements, RHS sampling
       +--> INACTIVE : #0 queued work
       +--> NBA      : non-blocking LHS updates commit
       +--> OBSERVED : assertions sample stable design values
       +--> REACTIVE : testbench/program reaction code
    
    If behavior looks impossible, ask: "Which region saw which value?"

    Related topics

    • SystemVerilog Language Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Datatype and Bit Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles