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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
    • Fork Join Puzzles
      • join vs join_any vs join_none
      • Loop Variable Capture in Detached Threads
      • wait fork Synchronization Point
      • disable Named Fork Scope
      • join_any Without Cleanup
      • Inner disable fork Does Not Kill Outer Sibling
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Fork Join Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Fork Join Puzzles
  5. join vs join_any vs join_none

VLSI DV Interview Puzzles · All levels

join vs join_any vs join_none

Give the timeline of all prints and identify which children survive each block.

On this page

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: Fork Join Puzzles

    Give the timeline of all prints and identify which children survive each block.

    Code

    p1.sv
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    module p1;
      initial begin
        fork
          begin #5  $display("%0t A", $time); end
          begin #10 $display("%0t B", $time); end
        join
        $display("%0t join_done", $time);
    
        fork
          begin #5  $display("%0t C", $time); end
          begin #10 $display("%0t D", $time); end
        join_any
        $display("%0t join_any_done", $time);
        disable fork;
    
        fork
          begin #5  $display("%0t E", $time); end
          begin #10 $display("%0t F", $time); end
        join_none
        $display("%0t join_none_done", $time);
        #1 disable fork;
      end
    endmodule

    Hint

    Analyze each fork block independently, but remember simulation time accumulates because they execute sequentially in one initial block.

    Step-by-step solution

    Diagram
    1) First block (`join`) waits for both children: A at t=5, B at t=10, then `join_done` at t=10.
    2) Second block starts at t=10: C at t=15, parent resumes at `join_any` and prints `join_any_done` at t=15, then `disable fork` kills D.
    3) Third block starts at t=15: `join_none_done` prints immediately at t=15, then parent waits #1 and kills both detached children at t=16 before E/F can print.

    Answer

    Answer: A@5, B@10, join_done@10, C@15, join_any_done@15, join_none_done@15; D/E/F never print

    Why candidates get it wrong

    People remember only 'parallel' and forget parent resumption semantics and explicit cleanup needs.

    Interviewer follow-up

    What changes if the third block removes `#1` and calls `disable fork;` immediately?

    Related topics

    • Back to Fork Join Puzzles

    • SystemVerilog Language Puzzles section

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    See also

    • wait fork Synchronization Point
    • disable Named Fork Scope
    • join_any Without Cleanup