SystemVerilog Language Puzzles: Tricky Q&A

Section Q&A

Rapid-fire questions an interviewer asks around SystemVerilog Language Puzzles. Answer out loud, then check yourself.

Q1. Why does `if (a == b)` with `logic` values sometimes skip the branch even when signals look visually close?

Answer: `==` is 4-state logical equality and can return x when either operand contains unknown bits. In an `if`, only 1 is true; 0 and x both behave as not-true. Use `===` when you need deterministic bit-exact comparisons including X/Z.

Trap: Assuming comparison operators always return only 0 or 1.

Q2. After `join_any`, why do some tests still print logs from the 'losing' child thread later?

Answer: `join_any` only unblocks the parent when one child completes; it does not terminate remaining children. Unless you explicitly synchronize or terminate them (`disable fork`, `wait fork`, process handles), leftover threads keep running and can race later phases.

Trap: Treating `join_any` as automatic cancellation semantics.

Q3. Why is repeated dynamic-array resize (`new[N](old)`) a common source of wrong expected data in interviews?

Answer: Each resize copies only the current prefix `min(old.size, N)` into a newly allocated array. Once truncated, removed elements are irrecoverable unless saved separately. Subsequent growth extends the already-truncated array with default values.

Trap: Thinking resize behaves like capacity growth while retaining all historical entries.

Q4. What practical bug does `$cast` prevent compared to static casts in polymorphic testbench code?

Answer: `$cast` performs runtime type checking and returns success/failure so code can branch safely before dereferencing fields. Static casts may compile even when runtime object is incompatible, hiding bad assumptions and causing fragile behavior.

Trap: Believing static handle type guarantees runtime object compatibility.