These puzzles target the places where SystemVerilog silently changes interpretation based on type: 4-state vs 2-state storage, signedness propagation, and operator-specific rules. Strong candidates can predict exact outputs by tracking width, sign, and unknown-bit semantics at every step.
1. X-Bit Comparisons and Mixed Arithmetic [Easy]
2. Signed vs Unsigned Comparison Trap [Medium]
3. Type Cast Controls Sign Extension [Medium]
4. Signed Part-Select Is Still Unsigned [Hard]
5. X Collapse into 2-State `int` [Medium]
6. Case Equality vs Wildcard Equality [Easy]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
time slot T
|
+--> ACTIVE : blocking statements, RHS sampling
+--> INACTIVE : #0 queued work
+--> NBA : non-blocking LHS updates commit
+--> OBSERVED : assertions sample stable design values
+--> REACTIVE : testbench/program reaction code
If behavior looks impossible, ask: "Which region saw which value?"