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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Case Equality vs Wildcard Equality
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. Case Equality vs Wildcard Equality

VLSI DV Interview Puzzles · All levels

Case Equality vs Wildcard Equality

For this value with an unknown bit, what do `==`, `===`, and `==?` return?

On this page

    Puzzle

    Difficulty: Easy · Puzzle 6 of 6 · Topic: Datatype and Bit Puzzles

    For this value with an unknown bit, what do `==`, `===`, and `==?` return?

    Code

    p6.sv
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    module p6;
      logic [3:0] v = 4'b10x1;
      initial begin
        $display("eq=%b", v == 4'b1001);
        $display("caseeq=%0d", v === 4'b10x1);
        $display("wild=%0d", v ==? 4'b1??1);
      end
    endmodule

    Hint

    `===` is exact 4-state match. `==?` treats wildcard bits in the pattern (RHS) as don't-care.

    Step-by-step solution

    Diagram
    1) `v == 4'b1001` returns x because the x bit affects normal logical equality.
    2) `v === 4'b10x1` returns 1 because every bit, including x, matches exactly.
    3) `v ==? 4'b1??1` returns 1 because RHS `?` bits are don't-care and only MSB/LSB are checked.

    Answer

    Answer: eq=x, caseeq=1, wild=1

    Why candidates get it wrong

    A common mistake is treating `==?` like `===` or assuming wildcarding happens on both operands.

    Interviewer follow-up

    What would `v ==? 4'b0??1` return, and why?

    Related topics

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

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    See also

    • X-Bit Comparisons and Mixed Arithmetic
    • Signed vs Unsigned Comparison Trap
    • Type Cast Controls Sign Extension