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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Case Equality vs Wildcard Equality
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. X Collapse into 2-State `int`

VLSI DV Interview Puzzles · All levels

X Collapse into 2-State `int`

Predict all lines and explain why `i` and `w` disagree about unknown data.

On this page

    Puzzle

    Difficulty: Medium · Puzzle 5 of 6 · Topic: Datatype and Bit Puzzles

    Predict all lines and explain why `i` and `w` disagree about unknown data.

    Code

    p5.sv
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    module p5;
      logic [3:0] l = 4'b10x1;
      int i = l;
      logic [31:0] w = l;
      initial begin
        $display("i=%0d", i);
        $display("w=%h", w);
        $display("w==32'h9 -> %b", w == 32'h0000_0009);
        $display("w===32'h9 -> %0d", w === 32'h0000_0009);
      end
    endmodule

    Hint

    `int` is 2-state, but `logic [31:0]` is 4-state. Compare `==` versus `===` separately.

    Step-by-step solution

    Diagram
    1) Assigning `l` into 2-state `int i` collapses x to 0, so `i` becomes 9.
    2) Assigning to 4-state `w` preserves unknown in low nibble, so hex print includes x.
    3) `w == 9` returns x because unknown participates in logical equality.
    4) `w === 9` returns 0 because case equality requires exact bit match and x does not equal 0 or 1.

    Answer

    Answer: i=9, w has an x nibble (for example 0000000x), `w==...` is x, `w===...` is 0

    Why candidates get it wrong

    Candidates memorize that X is preserved, but forget 2-state scalar types silently coerce it away.

    Interviewer follow-up

    What type change would keep `i` 32-bit wide but preserve X/Z information?

    Related topics

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

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    Next: Case Equality vs Wildcard Equality

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    Up nextCase Equality vs Wildcard Equality

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    See also

    • X-Bit Comparisons and Mixed Arithmetic
    • Signed vs Unsigned Comparison Trap
    • Type Cast Controls Sign Extension