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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
      • String Substr with Runtime Class Cast
      • putc/getc Index Semantics
      • Case-Sensitive vs Case-Insensitive Compare
      • Enum Safety with $cast
      • Failed Class Cast Leaves Old Handle
      • String Number Parsing Stops Early
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹SystemVerilog Language Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. String and Casting Puzzles

VLSI DV Interview Puzzles · All levels

String and Casting Puzzles

This set combines string API edge cases with runtime typing semantics. Interviewers use these to test whether you understand index-based string operations, conversion methods, and the exact success/failure behavior of `$cast`.

  • 6topics
  • 6lessons

Topics in this section

  1. 1String Substr with Runtime Class Cast1 lesson
  2. 2putc/getc Index Semantics1 lesson
  3. 3Case-Sensitive vs Case-Insensitive Compare1 lesson
  4. 4Enum Safety with $cast1 lesson
  5. 5Failed Class Cast Leaves Old Handle1 lesson
  6. 6String Number Parsing Stops Early1 lesson
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    About this puzzle set

    This set combines string API edge cases with runtime typing semantics. Interviewers use these to test whether you understand index-based string operations, conversion methods, and the exact success/failure behavior of `$cast`.

    Puzzles in this topic

    Diagram
    1. String Substr with Runtime Class Cast  [Easy]
    2. putc/getc Index Semantics  [Medium]
    3. Case-Sensitive vs Case-Insensitive Compare  [Easy]
    4. Enum Safety with $cast  [Medium]
    5. Failed Class Cast Leaves Old Handle  [Hard]
    6. String Number Parsing Stops Early  [Medium]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    SV scheduling regions at puzzle scale

    Diagram
    SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
    
    time slot T
       |
       +--> ACTIVE   : blocking statements, RHS sampling
       +--> INACTIVE : #0 queued work
       +--> NBA      : non-blocking LHS updates commit
       +--> OBSERVED : assertions sample stable design values
       +--> REACTIVE : testbench/program reaction code
    
    If behavior looks impossible, ask: "Which region saw which value?"

    Related topics

    • SystemVerilog Language Puzzles section

    • VLSI DV Interview Puzzles hub

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    See also

    • Datatype and Bit Puzzles
    • Fork Join Puzzles
    • Queue and Array Puzzles