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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
      • Handshake Hang: Missing item_done on One Branch
      • Missing run_phase Objection in Test
      • Wrong Phase: Starting Traffic in shutdown_phase
      • Handshake Violation: item_done Called Twice
      • Sequence get_response Stall
      • Virtual Sequence Waits on Event Never Triggered
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
    • Real Interview Rounds: End-to-End Debug Walkthrough
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Testbench Debug Puzzles: Why Did the Test Hang?
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Testbench Debug Puzzles: Why Did the Test Hang?
  5. Missing run_phase Objection in Test

VLSI DV Interview Puzzles · All levels

Missing run_phase Objection in Test

Some seeds appear as 'hangs' in CI because no PASS banner is printed and the harness waits. Simulation ends quickly, but traffic sequence did not complete. Identify the testbench bug.

On this page

    Puzzle

    Difficulty: Easy · Puzzle 2 of 6 · Topic: Testbench Debug Puzzles: Why Did the Test Hang?

    Some seeds appear as 'hangs' in CI because no PASS banner is printed and the harness waits. Simulation ends quickly, but traffic sequence did not complete. Identify the testbench bug.

    Code

    design.sv
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    class smoke_test extends uvm_test;
      \`uvm_component_utils(smoke_test)
      virtual task run_phase(uvm_phase phase);
        sanity_seq seq;
        seq = sanity_seq::type_id::create("seq");
        seq.start(env.agent.seqr);
        \`uvm_info("TEST", "run_phase done", UVM_LOW)
      endtask
    endclass

    Hint

    Decide who owns end-of-test lifetime while seq is running.

    Step-by-step solution

    Diagram
    1) Check phase timeline and see run_phase can complete before downstream monitors/scoreboard finish.
    2) Confirm no raise_objection/drop_objection around the sequence body.
    3) Add explicit objection in test run_phase or use sequence automatic phase objections intentionally.
    4) Re-run and verify test exits only after completion criteria is satisfied.
    5) Add a guard log that prints objection count at run_phase entry/exit.

    Answer

    Answer: Bug: test run_phase has no objection ownership, so runtime can end before intended completion flow. Fix: bracket seq.start with phase.raise_objection/drop_objection (or equivalent sequence objection policy).

    Why candidates get it wrong

    Candidates confuse this with scoreboard deadlock; the real issue is phase lifetime ownership.

    Interviewer follow-up

    When would you prefer automatic objections on the sequence versus explicit objections in the test?

    Related topics

    • Back to Testbench Debug Puzzles: Why Did the Test Hang?

    • Scenario & Debug Puzzles section

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    See also

    • Handshake Violation: item_done Called Twice
    • Sequence get_response Stall
    • Virtual Sequence Waits on Event Never Triggered