VLSI DV Interview Puzzles · All levels

Virtual Sequence Waits on Event Never Triggered

A virtual sequence waits on done_ev and hangs at end of traffic. Waveform shows DUT completed all transfers. Why is vseq still blocked?

Puzzle

Difficulty: Hard · Puzzle 6 of 6 · Topic: Testbench Debug Puzzles: Why Did the Test Hang?

A virtual sequence waits on done_ev and hangs at end of traffic. Waveform shows DUT completed all transfers. Why is vseq still blocked?

Code

systemverilog

class env extends uvm_env;
  monitor mon;
  scoreboard sb;
  virtual function void connect_phase(uvm_phase phase);
    // bug: monitor connected to old scoreboard instance
    mon.ap.connect(sb.shadow_imp);
  endfunction
endclass

class top_vseq extends uvm_sequence;
  virtual task body();
    start_subseqs();
    @(p_sequencer.env.sb.done_ev); // never triggers
  endtask
endclass

Hint

Validate analysis connections and which instance raises done_ev.

Step-by-step solution

diagram

1) Print topology and confirm monitor analysis port subscriber path.
2) Compare event trigger location with event wait location.
3) Detect that monitored transactions never reach the scoreboard instance the vseq watches.
4) Connect monitor to active scoreboard imp and trigger done_ev in the same instance.
5) Add an end-of-test check that flags zero scoreboard activity as configuration error.

Answer

Answer: Bug: virtual sequence waits on done_ev from one scoreboard instance while monitor writes to another. Fix: correct analysis port wiring and keep event trigger/wait in same live instance.

Why candidates get it wrong

Teams inspect DUT first, but this is pure TB connectivity.

Interviewer follow-up

How would you automatically validate critical TLM connections during build/connect?

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