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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
    • Testbench Debug Puzzles: Why Did the Test Hang?
      • Handshake Hang: Missing item_done on One Branch
      • Missing run_phase Objection in Test
      • Wrong Phase: Starting Traffic in shutdown_phase
      • Handshake Violation: item_done Called Twice
      • Sequence get_response Stall
      • Virtual Sequence Waits on Event Never Triggered
    • Deadlock Scenario Puzzles: Objection and Phase Stalls
    • Scoreboard Puzzles: Mismatch or Ordering Bug?
    • Real Interview Rounds: End-to-End Debug Walkthrough
    • Scenario & Debug Puzzles: Tricky Q&A
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Testbench Debug Puzzles: Why Did the Test Hang?
  1. Topics
  2. DV Interview Puzzles
  3. Scenario & Debug Puzzles
  4. Testbench Debug Puzzles: Why Did the Test Hang?
  5. Handshake Hang: Missing item_done on One Branch

VLSI DV Interview Puzzles · All levels

Handshake Hang: Missing item_done on One Branch

Regression hangs in 3/200 seeds. Last log says the sequence is blocked in finish_item(). Find the exact liveness bug and fix it without changing stimulus intent.

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    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Testbench Debug Puzzles: Why Did the Test Hang?

    Regression hangs in 3/200 seeds. Last log says the sequence is blocked in finish_item(). Find the exact liveness bug and fix it without changing stimulus intent.

    Code

    design.sv
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    class req_seq extends uvm_sequence #(my_item);
      \`uvm_object_utils(req_seq)
      virtual task body();
        my_item req;
        repeat (100) begin
          req = my_item::type_id::create("req");
          start_item(req);
          assert(req.randomize());
          finish_item(req);
        end
      endtask
    endclass
    
    class my_driver extends uvm_driver #(my_item);
      \`uvm_component_utils(my_driver)
      virtual task run_phase(uvm_phase phase);
        my_item req;
        forever begin
          seq_item_port.get_next_item(req);
          if (req.addr[0]) begin
            continue; // bug
          end
          drive_req(req);
          seq_item_port.item_done();
        end
      endtask
    endclass

    Hint

    Audit get_next_item/item_done pairing on every control-flow path, not just the common path.

    Step-by-step solution

    Diagram
    1) Reproduce with one seed and add driver logs around get_next_item/item_done including txn id.
    2) Observe iterations where req.addr[0] is 1 and code executes continue before item_done.
    3) Confirm sequencer waits forever because one request handshake is never closed.
    4) Refactor to call item_done exactly once for every get_next_item regardless of branching.
    5) Add an assertion or counter check that outstanding requests return to zero at end-of-test.

    Answer

    Answer: Bug: early continue skips item_done, so finish_item blocks. Fix: ensure one item_done per get_next_item in all branches (including error/skip branches).

    Why candidates get it wrong

    Teams often increase timeout first, masking the protocol-liveness bug and wasting debug cycles.

    Interviewer follow-up

    How would you instrument sequencer-driver latency so this class of bug is caught within 100 cycles?

    Related topics

    • Back to Testbench Debug Puzzles: Why Did the Test Hang?

    • Scenario & Debug Puzzles section

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    Next: Missing run_phase Objection in Test

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    See also

    • Wrong Phase: Starting Traffic in shutdown_phase
    • Handshake Violation: item_done Called Twice
    • Sequence get_response Stall