VLSI DV Interview Puzzles · All levels
Logic & Aptitude Puzzles: Tricky Q&A
Rapid-fire interview Q&A for Logic & Aptitude Puzzles.
Section Q&A
Rapid-fire questions an interviewer asks around Logic & Aptitude Puzzles. Answer out loud, then check yourself.
Q1. Why is the 9-ball puzzle solved in two weighings, not three?
Answer: A balance yields three outcomes per weighing. Two weighings provide 3^2=9 distinguishable outcome paths, matching nine candidates exactly.
Trap: Treating each weighing as binary and missing ternary information capacity.
Q2. In biased-coin fair-bit generation, why do we reject HH and TT?
Answer: Only HT and TH are equiprobable for any unknown bias p. Keeping HH/TT would skew outputs unless p were known.
Trap: Assuming unknown-bias outcomes are automatically symmetric.
Q3. Does adding one synchronizer flop improve CDC reliability linearly?
Answer: No. MTBF scales exponentially with added settling time (approximately exp(deltaT/tau)), which is why one stage can give huge gains.
Trap: Assuming CDC improvement is a fixed additive margin per flop.
Q4. A mismatch appears only on some seeds. What should be checked before editing DUT RTL?
Answer: First rule out TB observation races (sampling region, clocking block skew, handle reuse). Intermittent seed-only failures are often checker timing bugs.
Trap: Jumping directly into DUT logic changes without proving monitor/checker correctness.