VLSI DV Interview Puzzles · All levels

Randomization Always Fails: Hidden Unsat

A constraint block fails every randomize call. Find the logical contradiction.

Puzzle

Difficulty: Medium · Puzzle 6 of 6 · Topic: Debugging Riddles

A constraint block fails every randomize call. Find the logical contradiction.

Code

systemverilog

class pkt;
  rand bit [3:0] addr;
  constraint c {
    addr inside {[0:15]};
    addr[0] == 1'b1;   // odd
    addr % 4 == 0;     // multiple of 4
  }
endclass

Hint

Check parity implied by modulo condition.

Step-by-step solution

diagram

1) addr % 4 == 0 implies addr is divisible by 4, therefore LSB addr[0] must be 0.
2) Another constraint requires addr[0] == 1.
3) These cannot both hold, so solver has no legal solution.
4) Fix by relaxing one condition, e.g., use addr % 4 == 1 for odd values with fixed stride.

Answer

Answer: Constraint set is unsatisfiable: odd-number requirement conflicts with multiple-of-4 requirement.

Why candidates get it wrong

Debugging seed/tool settings before checking satisfiability algebraically.

Interviewer follow-up

How would you encode legal addresses as a weighted distribution instead?

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