Difficulty: Hard · Puzzle 2 of 6 · Topic: Debugging Riddles
FSM occasionally starts in X/illegal state after reset release on silicon-like timing, but many RTL sims pass. Identify root cause and fix.
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= IDLE;
else state <= next_state;
end
// TB deasserts rst_n at an arbitrary time not aligned to clk.Asynchronous assert is fine; asynchronous deassert is the risk.
1) Deasserting async reset near active clock edge can violate recovery/removal timing.
2) Different flops may observe reset release on different edges, causing illegal mixed state bits.
3) RTL may hide this due to optimistic event ordering; gate-level/real hardware can expose it.
4) Standard fix: async assert, sync deassert using a reset synchronizer in each clock domain.
5) Also ensure testbench releases reset on a clean clock edge for deterministic simulation.Answer: Bug is asynchronous reset deassert timing; synchronize reset release per clock domain.
Assuming passing RTL seeds proves reset strategy is robust.
How many sync flops do you choose for reset release and why?