VLSI DV Interview Puzzles · All levels
Scoreboard Sees Previous-Cycle Data
A few random seeds fail with scoreboard mismatch. Waveform shows DUT output is correct, but monitor appears one cycle stale. Find the likely bug.
Puzzle
Difficulty: Medium · Puzzle 1 of 6 · Topic: Debugging Riddles
A few random seeds fail with scoreboard mismatch. Waveform shows DUT output is correct, but monitor appears one cycle stale. Find the likely bug.
Code
systemverilog
always @(posedge clk) begin
txn.data = vif.data; // sampled immediately on edge
ap.write(txn);
endHint
Think simulation regions and NBA update timing.
Step-by-step solution
diagram
1) DUT flops typically update outputs via NBA after posedge active region.
2) Monitor also triggers on posedge in active region and can read old value before NBA commits.
3) That creates seed-dependent ordering/race symptoms when checker compares stale sampled data.
4) Fix by sampling in a clocking block input skew (#1step) or one delta later, or by transaction event after DUT update point.
5) Re-run multiple seeds to confirm mismatch disappears without changing DUT logic.Answer
Answer: This is a monitor sampling race, not a DUT bug; align monitor sample phase after DUT updates.
Why candidates get it wrong
Editing DUT datapath first and missing that observation timing is wrong.
Interviewer follow-up
How would you prove in logs that monitor sampled pre-NBA values?