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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
    • Debugging Riddles
      • Scoreboard Sees Previous-Cycle Data
      • Reset Release Causes Occasional X State
      • always_comb with NBA and Missing Else
      • UVM Analysis Port Handle Reuse
      • join_any Timeout Ghost Thread
      • Randomization Always Fails: Hidden Unsat
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Debugging Riddles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Debugging Riddles
  5. Scoreboard Sees Previous-Cycle Data

VLSI DV Interview Puzzles · All levels

Scoreboard Sees Previous-Cycle Data

A few random seeds fail with scoreboard mismatch. Waveform shows DUT output is correct, but monitor appears one cycle stale. Find the likely bug.

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    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Debugging Riddles

    A few random seeds fail with scoreboard mismatch. Waveform shows DUT output is correct, but monitor appears one cycle stale. Find the likely bug.

    Code

    design.sv
    1
    2
    3
    4
    always @(posedge clk) begin
      txn.data = vif.data;  // sampled immediately on edge
      ap.write(txn);
    end

    Hint

    Think simulation regions and NBA update timing.

    Step-by-step solution

    Diagram
    1) DUT flops typically update outputs via NBA after posedge active region.
    2) Monitor also triggers on posedge in active region and can read old value before NBA commits.
    3) That creates seed-dependent ordering/race symptoms when checker compares stale sampled data.
    4) Fix by sampling in a clocking block input skew (#1step) or one delta later, or by transaction event after DUT update point.
    5) Re-run multiple seeds to confirm mismatch disappears without changing DUT logic.

    Answer

    Answer: This is a monitor sampling race, not a DUT bug; align monitor sample phase after DUT updates.

    Why candidates get it wrong

    Editing DUT datapath first and missing that observation timing is wrong.

    Interviewer follow-up

    How would you prove in logs that monitor sampled pre-NBA values?

    Related topics

    • Back to Debugging Riddles

    • Logic & Aptitude Puzzles section

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    See also

    • always_comb with NBA and Missing Else
    • UVM Analysis Port Handle Reuse
    • join_any Timeout Ghost Thread