VLSI DV Interview Puzzles · All levels
Digital Logic Puzzles
Gate construction constraints, FSM/counter reasoning, and CDC reliability math.
About this puzzle set
Gate construction constraints, FSM/counter reasoning, and CDC reliability math.
Puzzles in this topic
diagram
1. Build XOR Using Only 2:1 MUXes [Medium]
2. AND/OR/NOT from One 2:1 MUX Each [Easy]
3. Minimum NAND Gates for XOR [Medium]
4. Overlapping 1011 Sequence Detector [Hard]
5. Mod-6 Counter Behavior Check [Medium]
6. Metastability MTBF Improvement Estimate [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.