Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • AND/OR/NOT from One 2:1 MUX Each
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
Loading lesson

‹Logic & Aptitude Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles

VLSI DV Interview Puzzles · All levels

Digital Logic Puzzles

Gate construction constraints, FSM/counter reasoning, and CDC reliability math.

  • 6topics
  • 6lessons

Topics in this section

  1. 1Build XOR Using Only 2:1 MUXes1 lesson
  2. 2AND/OR/NOT from One 2:1 MUX Each1 lesson
  3. 3Minimum NAND Gates for XOR1 lesson
  4. 4Overlapping 1011 Sequence Detector1 lesson
  5. 5Mod-6 Counter Behavior Check1 lesson
  6. 6Metastability MTBF Improvement Estimate1 lesson
On this page

    About this puzzle set

    Gate construction constraints, FSM/counter reasoning, and CDC reliability math.

    Puzzles in this topic

    Diagram
    1. Build XOR Using Only 2:1 MUXes  [Medium]
    2. AND/OR/NOT from One 2:1 MUX Each  [Easy]
    3. Minimum NAND Gates for XOR  [Medium]
    4. Overlapping 1011 Sequence Detector  [Hard]
    5. Mod-6 Counter Behavior Check  [Medium]
    6. Metastability MTBF Improvement Estimate  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • Logic & Aptitude Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Build XOR Using Only 2:1 MUXes

    Up next

    Up nextBuild XOR Using Only 2:1 MUXes

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Classic Brain Teasers
    • Probability Puzzles
    • Debugging Riddles