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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • AND/OR/NOT from One 2:1 MUX Each
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Digital Logic Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
  5. Overlapping 1011 Sequence Detector

VLSI DV Interview Puzzles · All levels

Overlapping 1011 Sequence Detector

Design a Mealy FSM that asserts hit for one cycle whenever input stream contains pattern 1011, with overlap allowed (e.g., 1011011 gives two hits). How many states are needed and why?

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    Puzzle

    Difficulty: Hard · Puzzle 4 of 6 · Topic: Digital Logic Puzzles

    Design a Mealy FSM that asserts hit for one cycle whenever input stream contains pattern 1011, with overlap allowed (e.g., 1011011 gives two hits). How many states are needed and why?

    Code

    design.sv
    typedef enum logic [1:0] {S0, S1, S10, S101} state_t;
    // S0: none matched, S1: saw 1, S10: saw 10, S101: saw 101
    // From S101 on input 1 -> hit=1 and next state S1 (overlap).

    Hint

    Each state should encode longest matched suffix that is also a prefix.

    Step-by-step solution

    Diagram
    1) Track matched prefix lengths of target 1011.
    2) Need states for suffixes: empty, '1', '10', '101' => 4 states.
    3) In S101, input 1 completes 1011 so hit=1.
    4) After detection, suffix '1' remains relevant for overlap, so next state is S1, not S0.
    5) This yields minimal Mealy implementation with 4 states.

    Answer

    Answer: Four states are sufficient and minimal: S0, S1, S10, S101.

    Why candidates get it wrong

    Resetting to S0 after a hit loses overlapping detections.

    Interviewer follow-up

    How does a Moore version change state count and output timing?

    Related topics

    • Back to Digital Logic Puzzles

    • Logic & Aptitude Puzzles section

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    See also

    • Build XOR Using Only 2:1 MUXes
    • AND/OR/NOT from One 2:1 MUX Each
    • Metastability MTBF Improvement Estimate