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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • AND/OR/NOT from One 2:1 MUX Each
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Digital Logic Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
  5. AND/OR/NOT from One 2:1 MUX Each

VLSI DV Interview Puzzles · All levels

AND/OR/NOT from One 2:1 MUX Each

Using only a 2:1 MUX primitive Y=S?D1:D0 and constants, derive NOT A, A AND B, and A OR B. Also state minimum MUX count per gate.

On this page

    Puzzle

    Difficulty: Easy · Puzzle 2 of 6 · Topic: Digital Logic Puzzles

    Using only a 2:1 MUX primitive Y=S?D1:D0 and constants, derive NOT A, A AND B, and A OR B. Also state minimum MUX count per gate.

    Code

    design.sv
    // NOT A : S=A, D1=0, D0=1
    // A&B   : S=A, D1=B, D0=0
    // A|B   : S=A, D1=1, D0=B

    Hint

    Treat select line as the controlling variable in Shannon expansion.

    Step-by-step solution

    Diagram
    1) NOT A: Y=A?0:1 = ~A.
    2) A AND B: Y=A?B:0 = A&B.
    3) A OR B: Y=A?1:B = A|B.
    4) Each mapping uses a single 2:1 MUX, so minimum count is 1 per gate.

    Answer

    Answer: NOT/AND/OR each require exactly one 2:1 MUX with proper constant wiring.

    Why candidates get it wrong

    Assuming NOT needs extra hardware beyond constants on data inputs.

    Interviewer follow-up

    Using only MUX + constants, what is minimal MUX count for NAND?

    Related topics

    • Back to Digital Logic Puzzles

    • Logic & Aptitude Puzzles section

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    See also

    • Overlapping 1011 Sequence Detector
    • Mod-6 Counter Behavior Check
    • Metastability MTBF Improvement Estimate