VLSI DV Interview Puzzles · All levels

Early Return Leaves Objection Raised

run_phase never ends. \`+UVM_OBJECTION_TRACE\` shows one sequence objection remains high. Pinpoint where objection symmetry is broken.

Puzzle

Difficulty: Medium · Puzzle 1 of 6 · Topic: Deadlock Scenario Puzzles: Objection and Phase Stalls

run_phase never ends. \`+UVM_OBJECTION_TRACE\` shows one sequence objection remains high. Pinpoint where objection symmetry is broken.

Code

systemverilog
class traffic_seq extends uvm_sequence #(my_item);
  \`uvm_object_utils(traffic_seq)
  bit enable_traffic;
  virtual task body();
    if (starting_phase != null)
      starting_phase.raise_objection(this);
    if (!enable_traffic)
      return; // bug: drop is skipped
    repeat (50) \`uvm_do(req)
    if (starting_phase != null)
      starting_phase.drop_objection(this);
  endtask
endclass

Hint

Any return/disable path after raise must still execute drop.

Step-by-step solution

diagram
1) Enable objection trace and identify owner component/object that never drops.
2) Trace sequence control flow for config paths where enable_traffic is 0.
3) Confirm return bypasses drop_objection.
4) Wrap raise/drop with a raised flag and guaranteed cleanup block.
5) Add lint/checklist item: no naked return after raise_objection.

Answer

Answer: Bug: raise_objection executes but return bypasses drop_objection. Fix: structurally guarantee drop in all exits (raised flag + final cleanup).

Why candidates get it wrong

Checking only default config misses deadlock path gated by runtime knobs.

Interviewer follow-up

Would you enforce objection symmetry with a reusable utility wrapper around sequence body?

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