VLSI DV Interview Puzzles · All levels

Replace Flag in Repeated set_type_override

Two type overrides are applied for the same base. Predict behavior with `replace=0` and `replace=1`.

Puzzle

Difficulty: Medium · Puzzle 3 of 6 · Topic: Factory Override Puzzles

Two type overrides are applied for the same base. Predict behavior with `replace=0` and `replace=1`.

Code

systemverilog

class base_item extends uvm_object;
  `uvm_object_utils(base_item)
  function new(string name="base_item"); super.new(name); endfunction
endclass
class item_a extends base_item;
  `uvm_object_utils(item_a)
  function new(string name="item_a"); super.new(name); endfunction
endclass
class item_b extends base_item;
  `uvm_object_utils(item_b)
  function new(string name="item_b"); super.new(name); endfunction
endclass

initial begin
  base_item::type_id::set_type_override(item_a::get_type(), 0);
  base_item::type_id::set_type_override(item_b::get_type(), 0);
  $display("first=%s", base_item::type_id::create("x").get_type_name());
  base_item::type_id::set_type_override(item_b::get_type(), 1);
  $display("second=%s", base_item::type_id::create("y").get_type_name());
end

Hint

Second call with `replace=0` does not overwrite existing mapping.

Step-by-step solution

diagram

1) First mapping base->item_a is installed.
2) Second call with `replace=0` keeps existing mapping unchanged.
3) `first` therefore prints `item_a`.
4) Third call with `replace=1` updates mapping to item_b, so `second` prints `item_b`.

Answer

Answer: Output is `first=item_a` then `second=item_b`.

Why candidates get it wrong

Candidates forget `replace` semantics and assume latest call always wins.

Interviewer follow-up

Why can hidden replace defaults create flaky tests across reused env code?

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