VLSI DV Interview Puzzles · All levels
Framework for Any Unseen Puzzle
A repeatable way to attack a SystemVerilog/DV puzzle you have never seen.
Five-step attack
Classify: language semantics, scheduling/timing, randomization, assertion, or coverage?
Pin the types/widths/signedness and the clock/sampling context.
Trace deterministically: value-by-value, or region-by-region for timing.
Name the single rule that decides the outcome.
State the exact answer, then the trap, then how a mutation would change it.
Key takeaways
Exact prediction beats hand-waving every time.
Every answer should reduce to one nameable rule.