VLSI DV Interview Puzzles · All levels
Scenario: Testbench Hang
A regression job intermittently stalls near end-of-test despite DUT waveforms appearing idle and reset clean. Logs show no fatal error, but simulation never exits under CI seeds.
Scenario
A regression job intermittently stalls near end-of-test despite DUT waveforms appearing idle and reset clean. Logs show no fatal error, but simulation never exits under CI seeds.
What to observe
Mismatch between expected test completion time and observed run timeout rate across nightly regressions.
Common traps
Assuming DUT deadlock first while missing a UVM objection leak in the environment.
Ignoring blocked mailbox/semaphore paths because basic smoke tests pass.
Adding coarse global timeouts instead of isolating the offending phase or process.