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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
    • Framework for Any Unseen Puzzle
    • Scenario: Testbench Hang
    • Scenario: Constraint No-Solution
    • Scenario: Vacuous Assertion Pass
    • Scenario: Coverage Not Closing
  • DV Puzzle Cheatsheet
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‹Interview Prep: Puzzle Rounds
  1. Topics
  2. DV Interview Puzzles
  3. Interview Prep: Puzzle Rounds
  4. Scenario: Testbench Hang

VLSI DV Interview Puzzles · All levels

Scenario: Testbench Hang

A regression job intermittently stalls near end-of-test despite DUT waveforms appearing idle and reset clean. Logs show no fatal error, but simulation never exits under CI seeds.

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    Scenario

    A regression job intermittently stalls near end-of-test despite DUT waveforms appearing idle and reset clean. Logs show no fatal error, but simulation never exits under CI seeds.

    What to observe

    Mismatch between expected test completion time and observed run timeout rate across nightly regressions.

    Common traps

    • Assuming DUT deadlock first while missing a UVM objection leak in the environment.

    • Ignoring blocked mailbox/semaphore paths because basic smoke tests pass.

    • Adding coarse global timeouts instead of isolating the offending phase or process.

    Related topics

    • Back to Interview Prep

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    See also

    • Scenario: Vacuous Assertion Pass
    • Scenario: Coverage Not Closing