VLSI DV Interview Puzzles · All levels
Scenario: Vacuous Assertion Pass
An SVA check reports clean passes in dashboard summaries, yet silicon-like stress traces reveal protocol behavior that should violate intent under burst corner conditions.
Scenario
An SVA check reports clean passes in dashboard summaries, yet silicon-like stress traces reveal protocol behavior that should violate intent under burst corner conditions.
What to observe
High assertion pass rate paired with low antecedent hit coverage in failing workload classes.
Common traps
Treating pass counts as proof of behavior without checking antecedent activation.
Using overly restrictive disable conditions that prevent property engagement.
Closing signoff on assertion status alone instead of correlating with cover properties.