These puzzles target write-write and read-write races that slip through otherwise clean RTL style. The focus is not just identifying races, but proving exact sampled values and timing outcomes.
1. Competing Active Writers on x [Medium]
2. Blocking Writer vs NBA Writer Same Signal [Medium]
3. False Mismatch from Active Sampling [Easy]
4. #0 Monitor Is Still Before NBA [Medium]
5. Lost Update in Forked Counter [Hard]
6. Two always_ff Writers, One Register [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
time slot T
|
+--> ACTIVE : blocking statements, RHS sampling
+--> INACTIVE : #0 queued work
+--> NBA : non-blocking LHS updates commit
+--> OBSERVED : assertions sample stable design values
+--> REACTIVE : testbench/program reaction code
If behavior looks impossible, ask: "Which region saw which value?"