VLSI DV Interview Puzzles · All levels
Blocking Writer vs NBA Writer Same Signal
For each edge, determine the active print and the final post-NBA value of s.
Puzzle
Difficulty: Medium · Puzzle 2 of 6 · Topic: Race Condition Puzzles
For each edge, determine the active print and the final post-NBA value of s.
Code
systemverilog
module tb;
bit clk = 0;
int s = 9;
always #5 clk = ~clk;
always @(posedge clk) begin
s = 1;
$display("[%0t A ACTIVE] s=%0d", $time, s);
end
always @(posedge clk) begin
s <= 0;
$display("[%0t B ACTIVE] scheduled s<=0", $time);
end
initial begin
repeat (2) begin
@(posedge clk);
$strobe("[%0t POST] s=%0d", $time, s);
end
$finish;
end
endmoduleHint
Blocking updates active state; NBA commits at end of slot.
Step-by-step solution
diagram
1) Active region may print A before B or B before A.
2) A always drives active s to 1 at some point in that region.
3) B always schedules s<=0 for NBA.
4) Postponed value after NBA is always s=0 each edge.Answer
Answer: Active print order can vary, but final s is deterministically 0 at t=5 and t=15 due to NBA commit.
Why candidates get it wrong
Confusing unstable active snapshots with final end-of-slot state causes wrong conclusions.
Interviewer follow-up
If B used blocking s = 0 instead, would final value stay deterministic?