Clocking blocks remove many races, but only when skew and cycle-delay semantics are understood precisely. These puzzles test sampling versus driving instants, plus `##1` expectations in clocking-domain assertions.
1. Why First Sample Sees Old grant [Medium]
2. Interpreting |=> ##1 in Clocking Domain [Hard]
3. output #1step Misses Current Edge [Medium]
4. input #0 vs input #1step Snapshot [Hard]
5. Raw @posedge Monitor vs @(cb) Monitor [Medium]
6. Mixing Direct Drive and cb Drive [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
time slot T
|
+--> ACTIVE : blocking statements, RHS sampling
+--> INACTIVE : #0 queued work
+--> NBA : non-blocking LHS updates commit
+--> OBSERVED : assertions sample stable design values
+--> REACTIVE : testbench/program reaction code
If behavior looks impossible, ask: "Which region saw which value?"