Difficulty: Medium · Puzzle 3 of 6 · Topic: Clocking Block Puzzles
When does seen_req become 1 if req is driven via clocking block output #1step at first cb event?
interface ifc(input bit clk);
logic req;
clocking drv_cb @(posedge clk);
default output #1step;
output req;
endclocking
endinterface
module tb;
bit clk = 0;
ifc vif(clk);
bit seen_req = 0;
always #5 clk = ~clk;
always @(posedge clk)
seen_req <= vif.req;
initial begin
@(vif.drv_cb);
vif.drv_cb.req <= 1;
@(posedge clk); $display("[%0t] seen_req=%0b", $time, seen_req);
@(posedge clk); $display("[%0t] seen_req=%0b", $time, seen_req);
$finish;
end
endmoduleoutput #1step drives just after the edge, too late for same-edge sequential sampling.
1) Drive at first cb event occurs one step after t=5 edge.
2) Sequential always @(posedge clk) at t=5 already sampled old req=0.
3) seen_req remains 0 at t=15 sample print.
4) It becomes 1 on next edge and is visible at t=25 print.Answer: seen_req updates one clock later than many expect: old at t=15 print, new at t=25 print.
Assuming output #1step behaves like output #0 hides one-cycle slips.
What skew would you choose for same-edge DUT sampling intent?