VLSI DV Interview Puzzles · All levels

Interpreting |=> ##1 in Clocking Domain

For a req pulse at cycle N, at which cycle must grant be 1 for this property to pass?

Puzzle

Difficulty: Hard · Puzzle 2 of 6 · Topic: Clocking Block Puzzles

For a req pulse at cycle N, at which cycle must grant be 1 for this property to pass?

Code

systemverilog

interface arb_if(input bit clk);
  logic req, grant;
  clocking cb @(posedge clk);
    default input #0 output #0;
    input req, grant;
  endclocking
endinterface

property p_req_to_grant;
  @(vif.cb) vif.cb.req |=> ##1 vif.cb.grant;
endproperty

ap: assert property (p_req_to_grant);

Hint

|=> already moves one cycle; ##1 adds another cycle.

Step-by-step solution

diagram

1) Antecedent samples req at cycle N.
2) |=> shifts consequent start to cycle N+1.
3) ##1 shifts grant check to cycle N+2.
4) Property requires grant at N+2, not N+1.

Answer

Answer: grant must be 1 at cycle N+2. Candidates often misread this as next-cycle (N+1) behavior.

Why candidates get it wrong

Double-counting cycle delay is a classic `##1` interview trap.

Interviewer follow-up

How would you rewrite for exactly next-cycle grant expectation?

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