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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
    • Race Condition Puzzles
    • Clocking Block Puzzles
      • Why First Sample Sees Old grant
      • Interpreting |=> ##1 in Clocking Domain
      • output #1step Misses Current Edge
      • input #0 vs input #1step Snapshot
      • Raw @posedge Monitor vs @(cb) Monitor
      • Mixing Direct Drive and cb Drive
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Clocking Block Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Clocking Block Puzzles
  5. Interpreting |=> ##1 in Clocking Domain

VLSI DV Interview Puzzles · All levels

Interpreting |=> ##1 in Clocking Domain

For a req pulse at cycle N, at which cycle must grant be 1 for this property to pass?

On this page

    Puzzle

    Difficulty: Hard · Puzzle 2 of 6 · Topic: Clocking Block Puzzles

    For a req pulse at cycle N, at which cycle must grant be 1 for this property to pass?

    Code

    arb_if.sv
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    interface arb_if(input bit clk);
      logic req, grant;
      clocking cb @(posedge clk);
        default input #0 output #0;
        input req, grant;
      endclocking
    endinterface
    
    property p_req_to_grant;
      @(vif.cb) vif.cb.req |=> ##1 vif.cb.grant;
    endproperty
    
    ap: assert property (p_req_to_grant);

    Hint

    |=> already moves one cycle; ##1 adds another cycle.

    Step-by-step solution

    Diagram
    1) Antecedent samples req at cycle N.
    2) |=> shifts consequent start to cycle N+1.
    3) ##1 shifts grant check to cycle N+2.
    4) Property requires grant at N+2, not N+1.

    Answer

    Answer: grant must be 1 at cycle N+2. Candidates often misread this as next-cycle (N+1) behavior.

    Why candidates get it wrong

    Double-counting cycle delay is a classic `##1` interview trap.

    Interviewer follow-up

    How would you rewrite for exactly next-cycle grant expectation?

    Related topics

    • Back to Clocking Block Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • input #0 vs input #1step Snapshot
    • Raw @posedge Monitor vs @(cb) Monitor
    • Mixing Direct Drive and cb Drive