VLSI DV Interview Puzzles · All levels

Raw @posedge Monitor vs @(cb) Monitor

Both monitors run every edge. Explain why they can print different grant values at the same $time.

Puzzle

Difficulty: Medium · Puzzle 5 of 6 · Topic: Clocking Block Puzzles

Both monitors run every edge. Explain why they can print different grant values at the same $time.

Code

systemverilog

interface ifc(input bit clk);
  logic req, grant;
  clocking cb @(posedge clk);
    default input #0 output #0;
    input grant;
    output req;
  endclocking
endinterface

module tb;
  bit clk = 0;
  ifc vif(clk);
  always #5 clk = ~clk;
  initial vif.req = 1;
  always @(posedge clk) vif.grant <= vif.req;

  always @(posedge clk)
    $display("[%0t RAW] grant=%0b", $time, vif.grant);

  always @(vif.cb)
    $display("[%0t CB ] grant=%0b", $time, vif.cb.grant);

  initial begin
    repeat (2) @(posedge clk);
    $finish;
  end
endmodule

Hint

Raw posedge monitor runs in active; clocking block input #0 aligns sampling after sequential update visibility.

Step-by-step solution

diagram

1) RAW monitor can print old grant in active before NBA commit.
2) CB monitor samples with clocking semantics and sees event-aligned value.
3) At t=5, RAW commonly shows 0 while CB shows 1.
4) They share same $time but not same scheduler region view.

Answer

Answer: Different region visibility causes mismatch: RAW sees pre-NBA snapshot, CB sees post-sequential sampled view.

Why candidates get it wrong

Same timestamp does not imply same simulation-region state.

Interviewer follow-up

Why is @(cb) preferred for UVM monitors over raw @(posedge clk)?

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