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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
    • Event Scheduling Puzzles
    • Race Condition Puzzles
    • Clocking Block Puzzles
      • Why First Sample Sees Old grant
      • Interpreting |=> ##1 in Clocking Domain
      • output #1step Misses Current Edge
      • input #0 vs input #1step Snapshot
      • Raw @posedge Monitor vs @(cb) Monitor
      • Mixing Direct Drive and cb Drive
    • Semaphore & Mailbox Puzzles
    • Concurrency & Timing Puzzles: Tricky Q&A
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • Interview Prep: Puzzle Rounds5
  • DV Puzzle Cheatsheet
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‹Clocking Block Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Concurrency & Timing Puzzles
  4. Clocking Block Puzzles
  5. input #0 vs input #1step Snapshot

VLSI DV Interview Puzzles · All levels

input #0 vs input #1step Snapshot

Two monitors sample the same grant with different input skews. Which one sees same-edge NBA-updated grant?

On this page

    Puzzle

    Difficulty: Hard · Puzzle 4 of 6 · Topic: Clocking Block Puzzles

    Two monitors sample the same grant with different input skews. Which one sees same-edge NBA-updated grant?

    Code

    ifc.sv
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    interface ifc(input bit clk);
      logic req, grant;
      clocking mon0 @(posedge clk);
        default input #0;
        input grant;
      endclocking
      clocking mon1 @(posedge clk);
        default input #1step;
        input grant;
      endclocking
    endinterface
    
    module tb;
      bit clk = 0;
      ifc vif(clk);
      always #5 clk = ~clk;
    
      initial vif.req = 1;
      always @(posedge clk) vif.grant <= vif.req;
    
      initial begin
        @(vif.mon0);
        $display("[%0t] mon0.grant=%0b mon1.grant=%0b", $time, vif.mon0.grant, vif.mon1.grant);
        $finish;
      end
    endmodule

    Hint

    input #0 samples at event (after NBA visibility), input #1step samples before edge.

    Step-by-step solution

    Diagram
    1) grant<=req commits in NBA on the first edge.
    2) mon0 input #0 samples value aligned with event and sees updated grant=1.
    3) mon1 input #1step sampled just before edge and still sees old grant=0.

    Answer

    Answer: mon0 sees 1 while mon1 sees 0 on that first event. Skew choice directly changes sampled truth.

    Why candidates get it wrong

    Using #1step for 'safety' can accidentally introduce one-cycle stale sampling.

    Interviewer follow-up

    Which skew is better for scoreboard checks against flopped DUT outputs and why?

    Related topics

    • Back to Clocking Block Puzzles

    • Concurrency & Timing Puzzles section

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    See also

    • Why First Sample Sees Old grant
    • Interpreting |=> ##1 in Clocking Domain
    • Mixing Direct Drive and cb Drive