VLSI DV Interview Puzzles · All levels
input #0 vs input #1step Snapshot
Two monitors sample the same grant with different input skews. Which one sees same-edge NBA-updated grant?
Puzzle
Difficulty: Hard · Puzzle 4 of 6 · Topic: Clocking Block Puzzles
Two monitors sample the same grant with different input skews. Which one sees same-edge NBA-updated grant?
Code
systemverilog
interface ifc(input bit clk);
logic req, grant;
clocking mon0 @(posedge clk);
default input #0;
input grant;
endclocking
clocking mon1 @(posedge clk);
default input #1step;
input grant;
endclocking
endinterface
module tb;
bit clk = 0;
ifc vif(clk);
always #5 clk = ~clk;
initial vif.req = 1;
always @(posedge clk) vif.grant <= vif.req;
initial begin
@(vif.mon0);
$display("[%0t] mon0.grant=%0b mon1.grant=%0b", $time, vif.mon0.grant, vif.mon1.grant);
$finish;
end
endmoduleHint
input #0 samples at event (after NBA visibility), input #1step samples before edge.
Step-by-step solution
diagram
1) grant<=req commits in NBA on the first edge.
2) mon0 input #0 samples value aligned with event and sees updated grant=1.
3) mon1 input #1step sampled just before edge and still sees old grant=0.Answer
Answer: mon0 sees 1 while mon1 sees 0 on that first event. Skew choice directly changes sampled truth.
Why candidates get it wrong
Using #1step for 'safety' can accidentally introduce one-cycle stale sampling.
Interviewer follow-up
Which skew is better for scoreboard checks against flopped DUT outputs and why?