Difficulty: Easy · Puzzle 3 of 6 · Topic: Race Condition Puzzles
The monitor reports mismatch even though RTL is correct. Explain the race and first mismatch time.
module tb;
bit clk = 0;
bit d = 1;
bit q = 0;
always #5 clk = ~clk;
always @(posedge clk) q <= d;
always @(posedge clk) begin
if (q !== d)
$display("[%0t] mismatch q=%0b d=%0b", $time, q, d);
end
initial begin
repeat (2) @(posedge clk);
$finish;
end
endmoduleBoth always blocks run in active; q update is deferred to NBA.
1) At t=5, q is still 0 in active while d=1, so monitor flags mismatch.
2) q<=d commits in NBA later in same slot, making q=1 after monitor already checked.
3) This is a sampling race in monitor placement, not a DUT bug.Answer: First mismatch appears at t=5 because monitor samples old q in active before NBA update.
Candidates often blame DUT sequential logic instead of monitor region placement.
Would using a clocking block input #0 or $strobe-based check remove this false failure?